The field of the invention is in the manufacturing processing of integrated circuit (IC) chips, including IC packages and dies with transistors, interconnects and other microscopic elements and structures, and processing of printed wiring boards. The field of the invention also involves the printed wiring boards, IC packages, and IC dies themselves, as well as smart power devices and controllers, digital computers and data processing and other electronic systems.
Without limiting the scope of the invention its background is described in connection with chip fabrication.
IC chips can be made with metalization and dielectric material, such as a CVD (chemical vapor deposition) oxide. Polyimides have also been proposed for the dielectric, see "Polyimides as; Interlayer Dielectrics for High-Performance Interconnections of Integrated Circuits" by R. J. Jensen in Polymers For High Technology, American Chemical Society, 1987, Chapter 40.
A U.S. Pat. No. 4,702,792 describes a method in which Polymeric material is patterned to form openings and spaces, which are then filled with conductive material. Excess conductive material is removed by chemical-mechanical polishing to expose the polymeric material.
A coassigned application Ser. No. 455,210 filed Dec. 22, 1989 discloses polyimide on the backside of an integrated circuit to prevent plastic encapsulated IC package cracking during surface mount, and that application is hereby incorporated herein by reference.
A problem of intermetal films is planarization or smoothing of the top surface to allow better deposition and definition of the subsequent metalization. Resist-etchback and spin-on-glass are techniques used to solve this problem, but both require additional processing.
Once the intermetal film is planar, vertical holes called vias are cut to allow connection between metal layers. The process for cutting vias involves deposition of photoresist, patterning, and etching of the film. Metal deposition into the vias is a problem, not to mention the complication of the fabrication process of forming vias and the problem is axacerbated as feature sizes decrease.
Raffel et al. in "Laser-formed connections using polyimide" Appl. Phys. Lett. 42(8), Apr. 15, 1983, pp. 705-6 described a technique with a layer of insulating polyimide overlying two metal conductors and the gap between them. When a shuttered argon ion laser beam was focused on the polyimide a crater was formed, leaving a deposit of conducting carbon.
Venkatesan et al. in "Ion beam irradiated via-connect through an insulating polymer layer" J. Appl. Phys. 55(4), Feb. 15, 1984, pp. 1212-1214 spun a 8000 angstrom thick film of Hunts' Positive Resist HPR-204 onto a silicon substrate coated with a 1000 angstrom layer of silver. The film was irradiated by a 2-MeV Ar+ argon ion beam through a molybdenum mask. Squares of metallization were evaporated on one column of dots. They observed an approximate 50% decrease in film thickness and stated that this was consistent with loss of some of the constituent elements, particularly oxygen and hydrogen. They stated that a similar process could also be attempted by putting a metal layer on the organic film and then irradiating the polymer through the top metallization layer. Further, they warned "However, a polymer that does not undergo substantial thickness change upon irradiation would be necessary to preserve the homogeneity of the upper metal layer." Hitherto, this problem has apparently remained unsolved. In Raffel et al. "A Wafer-Scale Digital Integrator Using Restructurable VLSI" IEEE Trans. Electron Devices, Vol. ED-32, No. 2, February 1985, pp. 479-486, a low power argon laser formed a vertical weld between two normally insulated metal layers. A link structure had a three-layer sandwich of first-level metal, link dielectric, and second-level metal. The dielectric was composed of 8000 Angstroms of amorphous silicon with 100 Angstrom protective barriers of SiO2 interposed between the silicon and metal layers. The laser pulse incident on top-level metal caused the AlSiCu alloy to melt, and a crater was formed as the metal flowed, exposing the amorphous silicon which then melted causing a mixing of melted aluminum and silicon. First-level metal then melted and a metallic aluminum-silicon alloy conducting path was created between first and second level metal, on the order of one ohm or less.
In the same Raffel et al. 1985 article, polyimide was also used as an intermetal insulator. The article explained that there were both advantages and disadvantages to using polyimide. In patterning the polyimide, holes were formed for normal vias between first- and second-level metal, and additional holes were patterned at each link site so that at these locations only the link insulator sandwich separated the two levels of metal. The article also stated that it was necessary, to provide windows in the polyimide for both first- and second-level metal cutting because exposure to a laser beam caused charring of polyimide. In the absence of a window, this left a conducting carbon residue typically providing a leakage path of a few thousand ohms across the cut in the conductor.
Due to the widespread applications of IC (integrated circuit) chips, improvement is desirable in their manufacture to provide even further alternative structures and processes, to further increase reliability and yields and to reduce costs.
IC chips are usually mounted on printed circuit boards. U.S. Pat. Nos. 4,853,277 and 4,702,792 describe a process for producing circuit boards. Printed circuit boards are widely used in electronic systems and often have IC chips mounted to them. Innovations in printed circuit board technology are also desirable to even further increase their usefulness and potential for accommodating high density electronic circuitry.